Semiconductor devices including peripherally located bond pads, intermediates thereof, and assemblies and packages including the semiconductor devices

ABSTRACT

A semiconductor device package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by forming a conductive via that extends substantially through a substrate blank and laterally across a street located adjacent to an outer periphery of at least one semiconductor device. Upon severing the substrate along the street and through the conductive via, at least one outer connector is formed at an outer edge of the semiconductor device. An outer connector may include a recess that at least partially receives a conductive column protruding from a support substrate. Assemblies may include the packages in stacked arrangement, without height-adding connectors.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 10/736,244,filed Dec. 15, 2003, which is a divisional of application Ser. No.10/183,820 filed Jun. 27, 2002, now U.S. Pat. No. 6,727,116, issued Apr.27, 2004.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates generally to packaged semiconductordevices with a low profile. More specifically, the invention pertains towafer-level packages having a true chip profile or both a chip profileand a chip footprint.

The dimensions of many different types of state-of-the-art electronicdevices are ever decreasing. To reduce the dimensions of electronicdevices, the structures by which the microprocessors, memory devices,other semiconductor devices, and other electronic components of thesedevices are packaged and assembled with carriers, such as circuitboards, must become more compact. In general, the goal is toeconomically produce a chip-scale package (CSP) of the smallest sizepossible, and with conductive structures, such as leads, pins, orconductive bumps, which do not significantly contribute to the overallsize in the X, Y, or Z dimensions, all while maintaining a very highperformance level.

One approach to reducing the sizes of assemblies of semiconductordevices and circuit boards has been to minimize the profiles of thesemiconductor devices and other electronic components upon carriersubstrates (e.g., circuit boards) so as to reduce the distances thesemiconductor devices protrude from the carrier substrates. Varioustypes of packaging technologies have been developed to facilitateorientation of semiconductor devices upon carrier substrates in thismanner.

Conventionally, semiconductor device packages are multilayeredstructures, typically including a bottom layer of encapsulant material,a carrier (e.g., leads, a circuit board, etc.), a semiconductor die, anda top layer of encapsulant material, for example. In addition, theleads, conductive bumps, or pins of conventional semiconductor devicepackages, which electrically connect such packages to carriersubstrates, as well as provide support for the packages, are sometimesconfigured to space the semiconductor device packages apart from acarrier substrate. As a result, the overall thicknesses of thesesemiconductor device packages and the distances the packages protrudefrom carrier substrates are greater than is often desired for use instate-of-the-art electronic devices.

Wafer-level packaging (WLP) refers to packaging of an electroniccomponent while it is still part of a wafer. The packages that areformed by WLP processes are generally considered to be “chip-sized”packages, at least with respect to the lateral X and Y dimensions, i.e.,“footprint,” but typically have somewhat enlarged profiles in the Zdimension due to the solder balls, pins, or other conductive structuresthat protrude therefrom. Likewise, modules of stacked dice may useinterdie connections comprising solder balls, pins, etc., whichsubstantially contribute to the overall Z dimension, i.e., profile.“Flip-chip” technology, as originating with controlled-collapse chipconnection (C-4) technology, is an example of an assembly and packagingtechnology that results in a semiconductor device being orientedsubstantially parallel to a carrier substrate, such as a circuit board.In flip-chip technology, the bond pads or contact pads of asemiconductor device are arranged in an array over a major surface ofthe semiconductor device. Flip-chip techniques are applicable to bothbare and packaged semiconductor devices. A packaged flip-chip typesemiconductor device, which typically has solder balls arranged in aso-called “ball grid array”(BGA) connection pattern, typically includesa semiconductor die and a carrier substrate, which is typically termedan “interposer.” The interposer may be positioned adjacent either theback side of the semiconductor die or the active (front) surfacethereof.

When the interposer is positioned adjacent the back side of thesemiconductor die, the bond pads of the semiconductor die are typicallyelectrically connected by way of wire bonds or other intermediateconductive elements to corresponding contact areas on a top side of theinterposer. These contact areas communicate with corresponding bumpedcontact pads on the back side of the interposer. This type of flip-chipassembly is positioned adjacent a higher-level carrier substrate withthe back side of the interposer facing the carrier substrate.

If the interposer is positioned adjacent the active surface of thesemiconductor die, the bond pads of the semiconductor die may beelectrically connected to corresponding contact areas on an opposite,top surface of the interposer by way of intermediate conductive elementsthat extend through one or more holes formed in the interposer. Again,the contact areas communicate with corresponding contact pads on theinterposer. In this type of flip-chip semiconductor device assembly,however, the contact pads are also typically located on the top surfaceof the interposer. Accordingly, this type of flip-chip assembly ispositioned adjacent a higher-level carrier substrate, such as a printedcircuit board, by orienting the interposer with the top surface facingthe carrier substrate.

In each of the foregoing types of flip-chip semiconductor devices, thecontact pads of the interposer are disposed in an array that has afootprint that mirrors an arrangement of corresponding terminals orother contact regions formed on a carrier substrate. Each of the bond(on bare flip-chip semiconductor dice) or contact (on flip-chippackages) pads and its corresponding terminal may be electricallyconnected to one another by way of a conductive structure, such as asolder ball, that also spaces the interposer some distance away from thecarrier substrate.

The space between the interposer and the carrier substrate may be leftopen or filled with a so-called “underfill” dielectric material thatprovides additional electrical insulation between the semiconductordevice and the carrier substrate. In addition, each of the foregoingtypes of flip-chip semiconductor devices may include an encapsulantmaterial covering portions or substantially all of the interposer and/orthe semiconductor die.

The thicknesses of conventional flip-chip type packages having ball gridarray connection patterns are defined by the combined thicknesses of thesemiconductor die, the interposer, the adhesive material therebetween,and the conductive structures (e.g., solder balls) that protrude abovethe interposer or the semiconductor die. As with the flat packages,conventional flip-chip type packages are often undesirably thick for usein small, thin, state-of-the-art electronic devices. Furthermore, use ofthis general construction method for producing a stacked multichipmodule (MCM) results in a relatively high-profile, large footprintdevice.

Thinner, or low-profile, flip-chip type packages have been developedwhich include interposers or other carriers with recesses that areconfigured to receive at least a portion of the profiles ofsemiconductor devices. While interposers that include recesses-forpartially receiving semiconductor devices facilitate the fabrication ofthinner flip-chip type packages, the semiconductor dice of thesepackages, as well as intermediate conductive elements that protrudebeyond the outer surfaces of either the semiconductor dice or theinterposers, undesirably add to the thicknesses of these packages.

U.S. Pat. No. 5,541,450 and 5,639,695, both issued to Jones et al.(hereinafter “the '450 and '695 Patents”), disclose another type offlip-chip type package, which includes an interposer with asemiconductor die receptacle extending completely therethrough. The '695Patent teaches a package that may be formed by securing a semiconductordie directly to a carrier substrate and electrically connecting theinterposer to the carrier substrate before the semiconductor die iselectrically connected to the interposer. The semiconductor die,intermediate conductive elements that connect bond pads of thesemiconductor die to corresponding contact areas on the interposer, andregions of the interposer adjacent the receptacle may then beencapsulated. While this method results in a very low-profile flip-chiptype package, the package cannot be tested separately from the carriersubstrate. As a result, if the package is unreliable, it may also benecessary to discard the carrier substrate and any other componentsthereon. Moreover, the packaging method of the '695 Patent complicatesthe process of connecting semiconductor devices and other electroniccomponents to a carrier substrate. In addition, it should be noted thatin order to obtain a low-profile package, it may be necessary tosacrifice footprint compactness. The footprint area of such alow-profile package may be significantly greater than the area of thesemiconductor die thereof.

Thus, there is a need for semiconductor device packages that havedimensions that closely resemble the corresponding dimensions of asemiconductor device of such packages, as well as for packaging methods.

SUMMARY OF THE INVENTION

In the present invention, semiconductor devices include bond pads, orouter connectors, that are located on one or more peripheral edgesthereof. The outer connectors, which facilitate electrical connection ofthe semiconductor device to a substrate, such as a test substrate or acarrier substrate (e.g., an interposer or a printed circuit board), maybe arranged on a peripheral edge of the semiconductor device in such away as to impart the semiconductor device with a castellated appearance.Optionally, the outer connectors may include recesses that extendsubstantially from one major surface of the semiconductor device toanother, opposite major surface of the semiconductor device.

By way of example only, the outer connectors may be fabricated byforming redistribution circuitry over active surfaces of semiconductordevices that have yet to be severed from a fabrication substrate, suchas a full or partial wafer of semiconductive material (e.g., silicon,gallium arsenide, indium phosphide, etc.) or a full or partial,so-called silicon-on-insulator (SOI) type substrate (e.g., asilicon-on-ceramic (SOC) substrate, silicon-on-glass (SOG) substrate,silicon-on-sapphire (SOS) substrate, etc.). The redistribution circuitryextends from bond pad locations on the active surface of eachsemiconductor device on the fabrication substrate to a boundary, or“street,” between that semiconductor device and an adjacentsemiconductor device. At the boundary, electrically conductive viaswhich extend substantially through the thickness of the substrate areformed. The electrically conductive vias may comprise a solid quantityof conductive material or have hollow portions extending substantiallyalong the lengths thereof. Upon severing the adjacent semiconductordevices from one another, which is typically referred to in the art as“dicing,” each conductive via is bisected, creating outer connectorsthat are positioned on the resulting peripheral edge of the singulatedor diced semiconductor device.

As outer connectors formed in this manner extend substantially from anactive surface to the back side of the semiconductor device, portions ofeach outer connector may be exposed at both the active surface and theback side of the semiconductor device. Accordingly, either the activesurface or the back side of a semiconductor device of the presentinvention may be joined and electrically connected to one or more othersemiconductor devices or semiconductor device components (e.g., testsubstrates, carrier substrates, etc.).

Assembly of a semiconductor device according to the present inventionwith another semiconductor device or semiconductor device component maybe accomplished without any significant intervening space between theassembled semiconductor devices or semiconductor device andsemiconductor device component. In assembling a semiconductor device ofthe present invention with another semiconductor device or asemiconductor device component, the outer connectors of thesemiconductor device and corresponding contacts of the othersemiconductor device or semiconductor device component are aligned, thenelectrically connected with one another. Accordingly, semiconductordevices that include such outer connectors may facilitate the formationof assemblies and packages with minimal footprints (X and Y dimensions)as well as a minimal profile (Z dimension).

An example of a semiconductor device assembly that may include more thanone semiconductor device that incorporates teachings of the presentinvention may comprise a so-called “multiple-chip module” of stackedconfiguration. Aligned, corresponding outer connectors of the two ormore stacked semiconductor devices may be conductively connected to oneanother, such as by solder or by conductive pins or other structuresthat are at least partially received within receptacles of the outerconnectors. As the outer connectors extend from the active surface tothe back side of each of the semiconductor devices and since electricalconnection may be effected at the peripheries of the semiconductordevices, the opposed back side and active surface of adjacentsemiconductor devices may be positioned very closely to one another.Thus, a multichip module according to the present invention may comprisea stack of a large number of dice or packages, while avoiding the use ofundesirable height-adding interdie connectors, such as solder balls,bond wires, and the like. As a result, a multichip module that includessemiconductor devices of the present invention may have a minimumprofile dimension (Z dimension).

Additionally, a multichip module that includes semiconductor devicesaccording to the present invention may include a support substrate whichhas a footprint which is substantially equal in size (i.e., X and Ydimensions) to or only slightly larger than the footprint of theremainder of the multichip module. The support substrate may includeconventional contacts (e.g., bond pads if the support substrate is aninterposer or another semiconductor device, terminals if the supportsubstrate is a circuit board, contact areas on leads if the supportsubstrate comprises leads, etc.) to which outer connectors of thesemiconductor devices are electrically connected. By way of exampleonly, each contact of the support substrate and the corresponding outerconnectors of the semiconductor devices may be electrically connected toone another (e.g., secured to a contact of the support substrate andlocated between adjacent surfaces of corresponding, adjacent outerconnectors and/or within recesses of corresponding, adjacent outerconnectors) by way of a conductive material (e.g., solder, a conductiveor conductor-filled elastomer, etc.), by way conductive pins or otherelongate conductive structures (e.g., upwardly standing wires) that aresecured to and protrude from the contact and that are at least partiallyreceived within receptacles of the corresponding outer connectors, orotherwise, as known in the art.

Other features and advantages of the present invention will becomeapparent to those of ordinary skill in the art through consideration ofthe ensuing description, the accompanying drawings, and the appendedclaims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

In the drawings, in which some dimensions may be exaggerated, exemplaryembodiments for carrying out the invention are illustrated:

FIG. 1 is a perspective view of a fabrication substrate with multiplesemiconductor devices fabricated thereon in accordance with teachings ofthe present invention;

FIG. 2 is a plan view of an enlarged portion of the exemplaryfabrication substrate of FIG. 1, with multiple semiconductor devicesfabricated thereon in accordance with teachings of the invention, eachsemiconductor device including bond pads that are arranged in-line alonga central portion of the semiconductor device, which bond pads areredistributed to outer connectors that are positioned on oppositeperipheral edges thereof;

FIG. 3 is a plan view of a semiconductor device according to the presentinvention following singulation thereof from the fabrication substrateof FIG. 2;

FIG. 4 is a plan view of a semiconductor device of the present inventionwhich includes bond pads positioned adjacent to one edge thereof, whichbond pads are redistributed to outer connectors on multiple peripheraledges of the semiconductor device;

FIG. 5 is a cross-sectional view through a singulated semiconductordevice of the present invention, taken along line 5-5 of FIG. 3;

FIGS. 6, 7, 8 and 9 are partial plan views of various exemplaryredistribution conductive tracing patterns along adjacent semiconductordevices on a fabrication substrate;

FIGS. 10, 11, 12 and 13 are partial plan views of the redistributionconductive tracing patterns of FIGS. 6, 7, 8, and 9, respectively,following patterning thereof and formation of full via holes therein inaccordance with the teachings of the invention;

FIG. 14 is an enlarged plan view of a portion of the boundary betweenadjacent semiconductor devices of FIG. 11, illustrating the effect ofsingulation of the two semiconductor devices from one another to formouter connectors in accordance with teachings of the invention;

FIG. 15 is an enlarged perspective view of an outer connector formed inaccordance with the teachings of the invention;

FIG. 16 is an enlarged perspective view of another embodiment of anouter connector formed in accordance with the teachings of theinvention;

FIG. 17 is a perspective view of a multichip module including stacked.semiconductor devices of the present invention;

FIG. 18 is an exploded perspective view of a multichip module thatincludes stacked semiconductor devices according to the presentinvention;

FIG. 19 is an enlarged cross-sectional view through a portion of asupport substrate for a multichip module in accordance with teachings ofthe invention; and

FIGS. 20, 21 and 22 are enlarged plan views of portions of outerconnectors of packages, illustrating differing configurations ofconductive elements for establishing electrical connections with theouter connectors.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIGS. 1 and 2, a fabrication substrate, which is alsoreferred to herein as a substrate blank 8, is shown. One side of thesubstrate blank 8 is selected as an active surface 18 and the oppositeside becomes the back side 19. A pattern of straight boundary lines orstreets 12 and 14 (individually referred to herein as streets 12A, 12B,12C, etc., and 14A, 14B, 14C, etc., respectively), which respectivelyextend in the X direction and Y direction, is delineated for subdivisionof the substrate blank 8 into a plurality of areas at which separatesemiconductor devices 16 are to be fabricated and further processed toform packages 10 (individually referred to as packages 10A, 10B, 10C,etc.). Streets 12 and 14 also comprise saw lines for the subsequentsingulation of each package 10 from other packages 10 that have beenfabricated on the substrate blank 8. For example, in FIG. 2, a package10E is shown as being surrounded by immediately adjacent packages 10A,10B, 10C, 10D, 10F, 10G, 10H and 10J that are carried upon the same,yet-to-be severed substrate blank 8.

Semiconductor devices 16 and, thus, assembled packages 10 that includesemiconductor devices 16, may comprise any type of device, such as amemory device (e.g., dynamic random access memory (DRAM), static randomaccess memory (SRAM), programmable memory (PROM), electrically erasableprogrammable memory (EEPROM), flash memory, etc.), a processor, or anyother type of semiconductor device known in the art. Semiconductordevice 16 includes bond pads 20 (see, e.g., FIGS. 2-5) that facilitateelectrical communication between the integrated circuitry (not shown)thereof and external electronic components, as known in the art. Bondpads 20 may be arranged on an active surface 18 of each semiconductordevice 16 in any suitable fashion known in the art, such as in-linealong a central portion of the semiconductor device 16 or an edge ofpackage 10 thereof, peripherally, or in an area array.

The fabrication of semiconductor devices 16 may be effected inaccordance with the desired end use of the assembled package 10 of whicheach semiconductor device is intended to be a part. An integratedcircuit (not shown) is formed in each semiconductor device 16 tointerface with the active surface 18, as known in the art. A widevariety of integrated circuit device elements may be used in thesemiconductor device 16 of a package 10, including, for example,conductors, resistors, transistors, capacitors, inductors, insulators,and the like. Fabrication processes are used which typically fall intothe groups known as layering, patterning, doping and heating, and manyspecific variations of each are well known. For example, useful layeringprocesses include various methods of oxidation, chemical vapordeposition (CVD), molecular beam epitaxy, physical vapor deposition(PVD), and other techniques.

In the exemplary embodiment depicted in FIG. 2, each semiconductordevice 16 on substrate blank 8 is provided with bond pads 20 tofacilitate electrical connection of the integrated circuitry (not shown)of that semiconductor device 16 with external components, such as othersemiconductor devices or electronic components. The bond pads 20 arelocated so as not to interfere with subsequently fabricated outerconnectors 31 (FIGS. 3-5) of a package 10 of which the semiconductordevice 16 is a part.

In addition to a semiconductor device 16 (FIG. 1), the packages 10A,10B, 10C, 10D, 10E, etc., on the substrate blank 8 each includeconductive traces 28 that extend between various bond pads 20 and, priorto severing the packages 10A, 10B, 10C, 10D, 10E, etc., from oneanother, corresponding conductive vias 30, such as vias 30A, 30B, 30C,which are depicted, by way of example only, as being annular in shape.The conductive vias 30 extend completely through the thickness of thesubstrate blank 8 and, thus, through the entire thickness of the package10 of which they will become a part. For each conductive via 30 that islocated between adjacent, functional semiconductor devices 16, aconductive trace 28 extends from a bond pad 20 of each of the adjacent,functional semiconductor devices 16 to that conductive via 30. Each ofthe conductive vias 30 is positioned along a street 12, 14 (in thisexample, streets 14A, 14B, 14C, etc.) on the substrate blank 8. Eachconductive via 30 also extends laterally into at least a portion of thesemiconductor devices 16 between which it is positioned. For example,packages 10E and 10F share conductive vias 30C on the boundary line 14Cbetween the two packages 10E and 10F. Package 10D also shares conductivevias 30B with package 10E.

Singulation of the packages 10 from one another and from the substrateblank 8 is effected by cutting the substrate blank 8 along boundarylines 12 and 14 thereon. As substrate blank 8 is cut along streets 12and 14, the full conductive vias 30 that are positioned on a cut street12, 14 are cut into outer connectors 31, which remain at the peripheraledges 22 of each of the singulated packages 10, as shown in FIG. 3. Apackage 10 which has been singulated from the substrate blank 8, or“wafer level,” of FIG. 2 has outer connectors 31 inlaid into oppositeperipheral edges 22, 24 of the package 10. As the conductive vias 30shown in FIG. 2 are annular in shape, each outer connector 31 shown inFIG. 3 may include a semicircular recess 40 formed therein, whichextends along the substantial height of the outer connector 31.

Also, as shown in FIG. 4, teachings of the present invention may beapplied to packages 50 that include semiconductor devices havingperipheral bond pads 20 positioned on the active surface 18, adjacent toa single edge 52 of the semiconductor device 16N. The outer connectors31 of the package 10N of which semiconductor device 16N is a part may beformed on one or more other peripheral edges 54 of the semiconductordevice 16N and connected to corresponding bond pads 20 by metallization,such as conductive traces 28, as illustrated in FIG. 4. Of course,semiconductor devices with bond pads 20 arranged in other connectionpatterns are also within the scope of the present invention, as arepackages 10 with outer connectors 31 that are arranged in connectionpatterns which differ from those illustrated in FIGS. 2-4.

FIG. 5 is a cross-sectional view of a portion of a package 10.Semiconductor device 16 of package 10 includes integrated circuits 42,although only a single integrated circuit 42 is schematically depictedin FIG. 5. Each integrated circuit 42 terminates at a bond pad 20 on theactive surface 18 of the semiconductor device 16. An upper insulativelayer, i.e., a dielectric layer 36, which is formed on the activesurface 18, provides some protection for the underlying integratedcircuit 42. Conductive traces 28 (again, only one is shown) are formedatop the dielectric layer 36 and extend from each bond pad 20 towardcorresponding via through-holes 38, which are located on a street 12, 14that defines a periphery of the semiconductor device 16. A secondinsulative layer, or dielectric coating 44, may be formed so as to coverat least a portion of the top 32 of package 10. The second dielectriccoating 44 may be formed before or after the via through-holes 38 areformed. A conductive via 30, which includes a quantity of conductivematerial, such as one or more layers of metal, conductive orconductor-filled elastomer, or the like, deposited in or on the surfacesof a via through-hole 38, may be located within each via through-hole38. An insulative lining 39 on the surfaces of each via through-hole 38may electrically isolate each conductive via 30 from substrate blank 8.As conductive vias 30 are positioned on a street 12, 14 that is commonto the package 10 and a neighboring, like package 10X on the substrateblank 8, each conductive via 30 may be temporarily shared betweenadjacent packages 10 and 10X. As depicted, the conductive via 30 willsubsequently be severed to form two or more outer connectors 31, each ofwhich includes a recess 40 formed therein. The back side 19 of thesemiconductor device 16 may be at least partially coated with a lowerprotective insulative layer 46, as known in the art.

Turning now to FIGS. 6, 7, 8, and 9, various exemplary configurations ofconductive traces 28, which are applied to the package tops 32 at thewafer level, are illustrated. The conductive traces 28, which may beconsidered to be redistribution metallization, extend generallylaterally from each bond pad 20 to a desired outer connector 31 (see,e.g., FIGS. 4 and 5) location at a periphery of the package 10 and maybe joined to conductive traces 28 of adjacent packages 10 at a street12, 14 therebetween. In each of FIGS. 6-9, portions of two adjacentwafer-level packages 10D and 10E are shown with an intervening street14. In FIG. 6, the conductive traces 28 have substantially uniformlywidths and extend between bond pads 20 on the two packages 10D and 10E,intersecting the street 14 between packages 10D and 10E.

The conductive traces 28 may be formed by a wide range of processesknown in the art. By way of example, one or more layers of conductivematerial, such as metal (e.g., aluminum, copper, gold, nickel, etc.),may be formed on package tops 32 by any suitable process, including,without limitation, chemical vapor deposition (CVD), physical vapordeposition (PVD) (e.g., sputtering or evaporation), electrolyticplating, electroless plating, and immersion plating techniques. Whilesuch a layer of conductive material may be formed before, simultaneouslywith, or following the introduction of conductive material into viathrough-holes 38 (see, e.g., FIGS. 10-13), in the embodiments that areshown in FIGS. 6-9, the layer of conductive material from which theconductive traces 28 are formed would be deposited prior to theformation of via through-holes 38 and, thus, prior to the introductionof conductive material into the via through-holes 38. Next, the layer ofconductive material may be patterned, as known in the art, such as byuse of mask and etch techniques.

In FIG. 10, the packages 10D, 10E of FIG. 6 are subjected to formationof via through-holes 38 at the intersections 66 of each conductive trace28 with boundary line or street 14. It can be seen that when the widths56 of conductive traces 28 are less than the diameters of thecorresponding via through-holes 38, the conductive trace 28 will onlycontact a portion of the outer periphery of its corresponding conductivevia 30 (FIG. 5). Thus, if desired, the conductive traces 28 may haveincreased widths 56 along a portion thereof or substantially the entirelengths thereof to more completely contact their correspondingconductive vias 30 (FIG. 5), as shown in FIGS. 7-9 and 11-13.

For example, in FIG. 7, each conductive trace 28N is shown with anenlargement 58N, i.e., a region of increased width, at the intersection66 of that conductive trace 28N with street 14. The width of enlargement58N is sufficient to completely peripherally surround an adjacent end ofa corresponding via through-hole 38 to be subsequently formedtherethrough, as shown in FIG. 11.

In FIGS. 8 and 12, conductive traces 28O are shown as includingdiamond-shaped enlargements 58O at intersections 66 along a street 14between two adjacent packages 10D, 10E. Adjacent diamond-shapedenlargements 58O may contact one another at areas 80, which aresubsequently removed when packages 10D and 10E are severed from oneanother, thereby electrically isolating adjacent enlargements 58O fromone another.

As depicted in FIGS. 9 and 13, the pattern of conductive traces 28′″ maybe formed to provide a conductive “street” 60 having boundary line orstreet 14 as a centerline. Portions of the street 60 may be etched orotherwise removed to form trace enlargements 58′″, and via through-holes38 formed at intersections 66, as shown in FIG. 13.

Referring again to FIG. 5, following the completion of conductive traces28 on a package, the package top 32 may be covered with a protectivedielectric coating 44, such as an adhesive-coated, dielectric film ortape, a quantity of dielectric polymer (e.g., by spin-on, screenprinting, doctor blade, or other suitable, known techniques),spin-on-glass (SOG), or the like.

The via through-holes 38 may be formed by any of a variety of knownprocesses, depending upon their heights 70 (i.e., the thickness of thesubstrate blank 8 and, thus, of the packages 10 in and between which thevia through-holes 38 are to be formed) (see FIG. 5), as well as theirdiameters 64 and the pitch 68 at which the via through-holes 38 arespaced (see FIG. 10). By way of example only, the via through-holes 38may be mechanically drilled (e.g., using multiple spindle machines asare used for forming holes in printed circuit boards or otherwise, asknown in the art) or formed by known laser-drilling techniques, by maskand etch processes, or as otherwise known in the art. When mechanicaldrilling processes are used to form via through-holes 38, subsequentcleaning and/or deburring processes may be effected, as known in theart, to remove a “smear” of dust that may be present on the edges of theconductive traces 28 or an enlargement 58 due to the heat generated bydrilling. Additionally, the via through-hole 38 may be etched back tofully expose the edges of the surrounding conductive trace 28 orenlargement 58. Of course, the usefulness of a particular method forforming via through-holes 38 in accordance with teachings of the presentinvention depends upon the desired dimensions of the via through-holes38, including their diameters 64 and heights 70, or height aspectratios. When each conductive via 30 is to be bisected, or severed intotwo outer connectors 31, the number of via through-holes 38 to be formedis one-half the number of outer connectors 31 to be formed.

Once the via through-holes 38 are formed, exposed semiconductivematerial at the surfaces thereof may be coated with an insulative lining39. The insulative lining 39 may be formed by known processes, such asby exposure of the surfaces of via though-holes 38 to oxidizingconditions, deposition of an insulative material (e.g., silicon dioxide,silicon nitride, silicon oxynitride, etc.) onto the surfaces of viathrough-holes 38, or any other suitable, known process.

As depicted in FIG. 14 with respect to packages 10D and 10E that arestill structurally connected to one another, or at the wafer level, aconductive via 30 may be formed in a via through-hole 38 by introducinga quantity of conductive material 29 onto at least the surfaces of eachvia through-hole 38. The conductive material 29 contacts at least edgeregions of a conductive trace 28 or enlargement 58 located adjacent toan opening of that via through-hole 38. While FIG. 14 depicts theconductive vias 30 as being annular in shape, the conductive vias 30 mayoptionally be substantially solid structures. The shapes of theconductive vias 30 may result from the methods by which conductivematerial 29 is introduced into the via through-holes 38. By way ofexample only, electroless deposition, immersion deposition, electrolyticdeposition, chemical vapor deposition (CVD), or physical vapordeposition (PVD) (e.g., sputtering, evaporation, etc.) techniques may beemployed. Alternatively, via through-holes 38 may be filled withconductive material 29 in the form of solder or another metal or metalalloy, conductive or conductor-filled elastomer, or other conductivematerials which have properties that make them suitable for use as outerconnectors 31 (e.g., low contact resistance with the materials ofadjacent conductive structures, good adhesion to adjacent materials,etc.). Examples of conductive materials 29 that may be used to formconductive vias 30 and, thus, outer connectors 31 (FIGS. 3-5) include,but are not limited to, nickel-plated copper, aluminum, and othersolder-compatible materials.

As shown in FIG. 14, the formation of conductive vias 30 is followed bysingulation of adjacent packages 10D and 10E from each other and fromother packages that are carried by the substrate blank 8; In thisinvention, the singulation process serves another purpose, namely, tosever each of a series of conductive vias 30 into portions and tothereby form outer connectors 31 (FIGS. 3-5) on at least one peripheraledge 22, 24 of each of the severed, adjacent packages 10D and 10E. Theouter connectors 31 may be semicylindrical, as shown in FIG. 15, orsemicircular if completely filled, as depicted in FIG. 16, depending, ofcourse, upon the degree to which the via through-hole 38 is coated orfilled with conductive material 29. Singulation may be accomplished bycutting with a wafer saw, for example. Wafer saws have a finite kerfwidth 74. Singulation of packages 10 from the substrate blank 8 willproduce separate packages 10 with kerf edges 72. The amount of materialremoved between adjacent packages 10, as well as the amount of materialremoved from each of the conductive vias 30, is defined, in part, by thekerf width 74. Accordingly, the width dimension of each outer connector31 may be defined, at least in part, by the kerf width 74 of a saw blade(not shown). Likewise, the width of each recess 40 formed in an outerconnector 31 may be at least partially defined by the kerf width 74. Theupper surface 76 and lower surface 78 of each outer connector 31 may besubstantially planar and have dimensions that facilitate attachment, bysolder, conductive or conductor-filled elastomer, or otherwise, to acontact area, such as a conductive land or a contact area of a lead, ofanother semiconductor device component, such as a carrier (e.g., aninterposer, a circuit board, leads, etc.), another packaged or baresemiconductor device, or the like.

Turning again to FIG. 12, it can be seen that, in singulation ofpackages 10D and 10E along street 14, the kerf width 74 may also removeareas 80 where enlargements 58O of adjacent conductive traces 28O arecontinuous with one another, such as the corners of the diamond-shapedenlargements 58O depicted in FIG. 12, thus separating and electricallyisolating adjacent conductive traces 28O from each other. Accordingly,when the kerf width 74 is sufficient to mechanically separate adjacentenlargements 58O, a further etching step to separate the enlargements58O from each other is unnecessary.

A package 10 with castellated edges 22, 24 and outer connectors 31 ofthe type described herein has an extremely low profile, which may beonly slightly larger than that of the semiconductor device 16 of such apackage 10. Furthermore, such a package 10 has a minimal footprint,which closely resembles the footprint of the semiconductor device 16thereof. In addition, due to its minimized size, the lengths ofconductive traces 28 that are required to redistribute the input/outputprovided by bond pads 20 to outer connectors 31 are minimized,facilitating the provision of a package 10 with electricalcharacteristics and signal integrity that are superior to those ofexisting semiconductor device packages.

In another aspect of the present invention, a plurality of packages 10may be assembled to form a so-called multichip module (MCM). In astacked MCM according to the present invention, packages 10 may bepositioned adjacent to one another with little or no spacingtherebetween, as may result from the use of discrete conductiveelements, such as solder balls, between adjacent packages, and with aminimized footprint, in contrast to the expanded footprints that arerequired when laterally extending, intermediate conductive elements,such as bond wires, conductive tape-automated bonding (TAB) elementscarried upon a dielectric polymer film, leads, or the like, are used toprovide electrical connections in conventional MCMs.

As depicted in FIGS. 17, 18 and 19, an exemplary multichip module 90, orsemiconductor device assembly, of the present invention is shown. Whilethe illustrated multichip module 90 includes four packages 10A-10D instacked arrangement, multichip modules with other arrangements and withother numbers of packages 10 are also within the scope of the presentinvention. By way of example only, stacked multichip modules 90 thatinclude a greater number of packages 10 would be particularly useful forhigh-capacity memory.

It will be appreciated that the multichip module 90 shown in FIGS. 17and 18 will comprise a stack of semiconductor packages 10 having anidentical pattern of outer connectors 31. However, depending upon theparticular package construction, same-width but shorter packages havingfewer outer connectors 31 may be incorporated in the multichip module90, provided that the partial pattern of outer connectors 31 fits withinthe larger connector pattern.

As shown, the packages 10 may be electrically interconnected andphysically supported by way of conductive columns 88 that are configuredand arranged to be at least partially received within aligned recesses40 of corresponding sets of outer connectors 31 of the stacked packages10. Conductive columns 88 are elongate members that may be formed from aconductive material (e.g., aluminum, copper, etc.) which willsubstantially retain their shapes when the outer connectors 31 ofpackages 10 are positioned adjacent thereto. Thus, each conductivecolumn 88 acts as a common lead for each of the outer connectors 31 of aset.

Each conductive column 88 is secured to (e.g., by solder, reflowing aportion thereof to secure the same to a terminal, etc.) and protrudesfrom a corresponding conductive member 100 (e.g., a terminal, conductivematerial-lined recess, etc.) of a support substrate 82 of the multichipmodule 90. In the exemplary embodiment of a circuit board (e.g., FR-4resin, BT resin, etc.) type support substrate 82 depicted in FIGS. 17,18, and 19, the conductive columns 88 are shown as being mounted inapertures 98 formed in the support substrate 82. The support substrate82 may alternatively comprise an interposer (which may be formed fromceramic, glass, plastic, insulator-lined silicon, etc.), leads, anothersemiconductor device, a test substrate, or any other known, suitabletype of substrate. Each conductive column 88 is electrically connectedto a portion of a corresponding conductive trace 92 that is located ator proximate to the end of the aperture 98 opposite that from which theconductive column 88 protrudes, which conductive trace 92 is carried bythe bottom surface 86 of the support substrate 82. Each conductive trace92 leads to a corresponding conductive structure, such as leads,leadless chip carrier (LCC) terminals, plug-in type connectors, ordiscrete conductive elements (i.e., balls 84N (FIGS. 18, 19), bumps,pillars, columns, pins 84 (FIG. 17), or other structures or conductivematerial), which are shown as being arranged in a so-called ball gridarray (BGA) connection pattern. In FIG. 17, the conductive structuresare shown as an array of pins 84, or “pin-grid-array”(PGA), while in theexploded view of FIG. 18, a ball-grid-array (BGA) of solder balls 84N isdepicted. As an alternative to including conductive traces 92 that arecarried by the bottom surface 86 of the support substrate 82, conductivetraces may be carried on the upper surface 85 of the support substrate82, internally within the support substrate 82, or in some combinationthereof, in which case conductive vias may be positioned at one or morelocations along the lengths of the conductive traces 92.

As an example of a method for forming the conductive columns 88, a wire(e.g., a gold or aluminum wire) may be drawn by use of a wire bondingcapillary, as known in the art. Such a wire may have a generallycircular cross-section, although conductive columns 88 having any othersuitable cross-section, taken transverse to the lengths thereof, arealso within the scope-of the present invention. By way of example only,and as shown in FIG. 21, the cross-section of a conductive column 88Nincorporating teachings of the present invention may be semicircular.Such a conductive column 88N could be used to form an assembly ofstacked packages 10 that is substantially chip-scale with respect toboth footprint and profile.

As noted above, the conductive column 88N may have transversecross-sectional dimensions (e.g., a diameter 102) that substantiallymatch or are slightly smaller than the complementary dimensions (e.g., adiameter 41; FIG. 22) of a recess 40 formed in the outer connector 31 towhich the conductive column 88 corresponds. This is illustrated in thepackage 10 of FIG. 20. As depicted in FIG. 22, a castellation column 88Omay alternatively have a cross-section which is circular but with adiameter 102 less than the diameter 41 of the recess 40 formed in thecorresponding outer connector 31.

As shown in FIG. 19, slippage of the conductive column 88 in itscorresponding aperture 98 may be avoided by use of a stop collar 94 onthe conductive column 88, and by solder attachment to adjacent portionsof conductive traces 92 on the bottom surface 86 of the supportsubstrate 82.

If desired (e.g., in packages that include outer connectors 31 arrangedalong only one or two adjacent peripheral edges 22, 24 thereof),conductive columns 88 may be secured to their outer connectors 31. Oneexample of the manner in which a conductive column 88 may be secured toa set of corresponding outer connectors 31 includes the use of aconductive adhesive, such as solder, another metal or metal alloy, aconductive or conductor-filled elastomer, or the like, which may bepositioned between a conductive column 88 and each of its correspondingouter connectors 31, around an outer periphery of the conductive column88 and in contact with lateral edges of each of the outer connectors 31that corresponds thereto, or in a combination of these locations.Optionally, the conductive columns 88 may be coated with tin to enhanceconnection to the outer connectors 31 in this manner. As anotherexample, a nonconductive material may be disposed around a surface ofeach conductive column 88 that does not contact outer connectors 31, aswell as to a peripheral edge 22, 24 of each package 10 of the multichipmodule 90, to maintain contact and, thus, an electrical connectionbetween each conductive column 88 and its corresponding outer connectors31.

Of course, when support substrate 82 comprises a test substrate, it maynot be desirable to bond or otherwise permanently secure the conductivecolumns 88 to their corresponding outer connectors 31, as temporary,reversible electrical connections are desired.

Following assembly of the support substrate 82 with all the packages 10in the stack and the establishment of contact between conductive columns88 and corresponding sets of outer connectors 31, the conductive columns88 may be cut, or trimmed, to remove any excess portion extending beyondthe uppermost package 10. The conductive columns 88 may alternatively beprovided with a length that corresponds to the height at which packages10 are to be stacked in the multichip module 90.

As described above, the multichip module 90 may be readily fabricatedusing processes and equipment which are widely used or known in theelectronics industry. The package 10 of the present invention may have atotal thickness of less than about 1 mm, making the package 10 suitablefor use in compact electronic devices, such as cellular telephones,handheld computers, and portable computers, where such low profilepackages are required or desired. The multichip module 90 of theinvention will likewise have a relatively low profile, making itsuitable for the same types of devices.

Although the foregoing description contains many specifics, these shouldnot be construed as limiting the scope of the present invention, butmerely as providing illustrations of some exemplary embodiments.Similarly, other embodiments of the invention may be devised which donot depart from the spirit or scope of the present invention. Featuresfrom different embodiments may be employed in combination. The scope ofthe invention is, therefore, indicated and limited only by the appendedclaims and their legal equivalents, rather than by the foregoingdescription. All additions, deletions, and modifications to theinvention, as disclosed herein, which fall within the meaning and scopeof the claims are to be embraced thereby.

1. An intermediate semiconductor device structure, comprising: asubstrate blank; at least two semiconductor devices fabricated on thesubstrate blank, the at least two semiconductor devices positionedadjacent to one another and separated from one another by way of astreet extending at least partially across the substrate blank; at leastone through-hole formed substantially through the substrate blank at thestreet; a first conductive trace extending from a bond pad of a firstsemiconductor device of the at least two semiconductor devices to the atleast one through-hole; and a second conductive trace extending from abond pad of a second semiconductor device of the at least twosemiconductor devices to the at least one through-hole.
 2. Theintermediate semiconductor device structure of claim 1, wherein the atleast one through-hole has a dimension perpendicular to a direction inwhich the street extends which exceeds a width of a cut to be made alongthe street to sever the first and second semiconductor devices from oneanother.
 3. The intermediate semiconductor device structure of claim 1,further comprising: at least one conductive via in the at least onethrough-hole.
 4. The intermediate semiconductor device structure ofclaim 3, wherein the at least one conductive via includes a hollowregion extending substantially along a height thereof.
 5. Theintermediate semiconductor device structure of claim 4, wherein thehollow region has a dimension perpendicular to a direction in which thestreet extends which exceeds a width of a cut to be made along thestreet to sever the first and second semiconductor devices from oneanother.
 6. The intermediate semiconductor device structure of claim 1,further comprising: an enlargement connecting ends of the first andsecond conductive traces and surrounding a periphery of an opening ofthe at least one through-hole.
 7. The intermediate semiconductor devicestructure of claim 1, comprising: a plurality of through-holes locatedalong the street; a plurality of first conductive traces extending fromcorresponding bond pads of the first semiconductor device tocorresponding through-holes of the plurality of through-holes; and aplurality of second conductive traces extending from corresponding bondpads of the second semiconductor device to corresponding through-holesof the plurality of through-holes.
 8. The intermediate semiconductordevice structure of claim 1, further comprising: an insulative layer orstructure beneath at least the first conductive trace.
 9. Theintermediate semiconductor device structure of claim 1, furthercomprising: an insulative layer covering at least the first conductivetrace and the bond pads of the first and second semiconductor devices.10. The intermediate semiconductor device structure of claim 1, furthercomprising: a back side insulative layer substantially covering a backside of the substrate blank.
 11. A semiconductor device assembly,comprising: a support substrate; at least one conductive columnprotruding from the support substrate; at least one semiconductor deviceincluding an outer connector on a peripheral edge thereof positionedlaterally adjacent to and in electrical communication with the at leastone conductive column, the outer connector having a height that extendssubstantially across a height of the peripheral edge, the outerconnector including: opposite surfaces exposed at the active surface anda back side of the semiconductor device; and a recess extendingsubstantially from one of the opposite surfaces to another of theopposite surfaces.
 12. The semiconductor device assembly of claim 11,wherein the support substrate comprises at least one of a circuit board,an interposer, leads, and another semiconductor device.
 13. Thesemiconductor device assembly of claim 11, wherein the at least oneconductive column is in electrical communication with a conductivestructure of the support substrate.
 14. The semiconductor deviceassembly of claim 13, wherein the at least one conductive column issecured to the conductive structure.
 15. The semiconductor deviceassembly of claim 14, wherein at least one of solder, another metal ormetal alloy, a conductive elastomer, and a conductor-filled elastomersecures the at least one conductive column to the conductive structure.16. The semiconductor device assembly of claim 13, wherein an end of theat least one conductive column is positioned within an aperture formedin the support substrate, at least a portion of the conductive structurebeing located adjacent to the aperture.
 17. The semiconductor deviceassembly of claim 16, wherein at least the portion of the conductivestructure contacts a portion of the end of the at least one conductivecolumn.
 18. The semiconductor device assembly of claim 16, wherein aquantity of conductive material contacts both the at least oneconductive column and the conductive structure.
 19. The semiconductordevice assembly of claim 18, wherein the quantity of conductive materialcomprises at least one of solder, another metal or metal alloy, aconductive elastomer, and a conductor-filled elastomer.
 20. Thesemiconductor device assembly of claim 11, wherein the outer connectorof the at least one semiconductor device includes a recess extendingsubstantially along a length thereof.
 21. The semiconductor deviceassembly of claim 20, wherein the recess is configured to at leastpartially receive the at least one conductive column.
 22. Thesemiconductor device assembly of claim 11, wherein the at least oneconductive column and the outer connector are secured in electricalcommunication with one another.
 23. The semiconductor device assembly ofclaim 22, wherein a quantity of conductive material secures the at leastone conductive column and the outer connector in electricalcommunication with one another.
 24. The semiconductor device assembly ofclaim 23, wherein the conductive material comprises at least one ofsolder, another metal or metal alloy, a conductive elastomer, and aconductor-filled elastomer.
 25. The semiconductor device assembly ofclaim 11, comprising a plurality of semiconductor devices in stackedarrangement.
 26. The semiconductor device assembly of claim 25, whereinadjacent active surfaces and back sides of adjacently positionedsemiconductor devices of the plurality of semiconductor devices aresubstantially electrically isolated from one another.
 27. Thesemiconductor device assembly of claim 25, wherein corresponding outerconnectors of at least some of the plurality of semiconductor devicesare in alignment with one another.
 28. The semiconductor device assemblyof claim 27, wherein aligned outer connectors of the at least some ofthe plurality of semiconductor devices include recesses therein.
 29. Thesemiconductor device assembly of claim 28, wherein the recesses arein-line with one another and at least partially receive the at least oneconductive column.
 30. The semiconductor device assembly of claim 25,wherein the at least one conductive column has a height that issubstantially equal to a stack height of the plurality of semiconductordevices.
 31. The semiconductor device assembly of claim 11, comprising aplurality of conductive columns protruding-from the support substrate.32. The semiconductor device assembly of claim 31, wherein each of theplurality of conductive columns is located so as to be positionedadjacent to a single peripheral edge of the at least one semiconductordevice.
 33. The semiconductor device assembly of claim 31, wherein theplurality of conductive columns are located so as to be positionedadjacent to more than one peripheral edge of the at least onesemiconductor device.